135 lines
4.0 KiB
TeX
135 lines
4.0 KiB
TeX
\section{CMOS Gatter}
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High Pegel ''H'': 0.9-0.7V \qquad Low Pegel ''L'': 0.15-0V \medskip
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\begin{minipage}{0.48\linewidth}
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\subsubsection{NMOS}
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\begin{center}
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\begin{circuitikz}[european]
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\node[circ, label=90:{\small $V_{DD} = 0.8 \si{\volt}$}](origin) at (0,0) {};
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\node[thick, nmos, anchor=D] (nmos1) at(0, -2) {}
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(nmos1.gate) node[anchor=east] {G}
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(nmos1.drain) node[anchor=west, yshift=-0.15cm] {D}
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(nmos1.source) node[anchor=west,yshift=+0.15cm] {S};
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\draw[thick]
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(origin)
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to[R=$R$] (0,-1.8) node[circ] (ybase) {}
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to[] (0, -2);
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\draw[thick] (nmos1.S) -- (0, -4) coordinate(gnd);
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\path[draw] (ybase) --++(right:10mm) node[point, label=0:Y] {};
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\path[draw, very thick] (-0.25, -4) -- (gnd) -- (0.25, -4);
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\end{circuitikz} \medskip
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\begin{tabular}{c|c|c}
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G & Schalter & Y \\
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\hline
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0 & offen & 1 \\
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1 & zu & 0
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\end{tabular}
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\end{center}
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\end{minipage}
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\vline
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\begin{minipage}{0.48\linewidth}
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\subsubsection{PMOS}
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\begin{center}
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\begin{circuitikz}[european]
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\coordinate (gnd) at (0, -4);
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\node[circ, label=90:{\small $V_{DD} = 0.8 \si{\volt}$}] (vdd) at (0,0) {};
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\node[pmos, thick] (pmos) at (0, -1){}
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(pmos.gate) node[anchor=east] {G}
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(pmos.source) node[anchor=west,yshift=-0.15cm] {S}
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(pmos.drain) node[anchor=west, yshift=+0.15cm] {D};
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\draw[thick] (gnd)
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to[R=$R$] (0, -2)
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-- (0, -2) node[circ] (ybase) {}
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-- (pmos.D);
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\draw[thick] (pmos.S) -- (vdd);
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\path[draw] (ybase) --++(right:10mm) node[point, label=0:Y] {};
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\path[draw, very thick] (-0.25, -4) -- (gnd) -- (0.25, -4);
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\end{circuitikz} \medskip
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\begin{tabular}{c|c|c}
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G & Schalter & Y \\
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\hline
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0 & zu & 1 \\
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1 & offen & 0
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\end{tabular}
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\end{center}
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\end{minipage} \medskip
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Zustand NN: Potential an Source unbestimmt, ''free floating''
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\subsection{Konstruktion von CMOS-Gatter}
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CMOS-Gatter benötigen \emph{pro} Eingang 1 NMOS + 1 PMOS. \medskip
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Sie bestehen aus zwei ergänzenden Schaltungsteilen:
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\begin{center}
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\begin{minipage}{0.3\linewidth}
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\begin{center}
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\begin{tikzpicture}
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\node[circ, label=90:{\small $V_{DD} = 0.8 \si{\volt}$}] at (0,0) (origin) {};
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\node[draw, dotted](pmos) at(0,-0.5) {PMOS};
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\node[draw, dotted](nmos) at (0, -1.5) {NMOS};
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\coordinate(gnd) at (0, -2){};
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\draw[] (origin) -- (pmos)
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(pmos) -- (nmos)
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(nmos) -- (gnd);
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\path[draw] (0,-1) --++(right:5mm) node[fill = white] {Y};
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\path[draw, thick] (-0.25, -2) -- (gnd) -- (0.25, -2);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\begin{minipage}{0.55\linewidth}
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\begin{flushleft}
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\begin{tabular}{l l}
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Pull-u\textcolor{red}{p} Schaltung: & \textcolor{red}{P}MOS \\
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Pull-dow\textcolor{red}{n} Schaltung: & \textcolor{red}{N}MOS \\
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\end{tabular}
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\end{flushleft}
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\end{minipage}
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\end{center}
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\subsubsection{Funktionsgleichung CMOS-Gatter}
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\begin{tabular}{l l l}
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Pull-Up: & $Y_{\text{pu}} = 1$ & Eingänge Invertiert \\
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Pull-Down: & $Y_{\text{pd}} = 0$ & Eingänge nicht Invertiert \\
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\end{tabular}
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\begin{center}
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\eqbox{$Y_{\text{pu}} = \overbrace{\underbrace{(\not{A} \land \not{B})}_{\text{Seriell} } \lor \not{C}}^{\text{Paralell} } \quad \Leftrightarrow \quad$
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$Y_{\text{pd}} = \overbrace{\overline{\underbrace{(A \lor B)}_{\text{Paralell} } \land C}}^{\text{Seriell} }$}
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\includegraphics[width = 0.32\textwidth]{images/pnmosDetConv.png}
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\end{center}
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\subsubsection{Umwandlung zwischen Pull-up und Pull-down}
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\begin{enumerate}
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\item Schaltung in Parallele und Serielle Blöcke zerlegen
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\item Umwandeln: Parallele $\rightleftharpoons$ Serielle Blöcke
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\item 1),2) wiederholen bis einzelnen Transistoren übrig sind
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\item Umwandeln: PMOS $\rightleftharpoons$ NMOS
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\item Schaltungstyp entsprechend Y, GND bzw. VDD setzen
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\end{enumerate} \medskip
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\includegraphics[width = 0.3\textwidth]{images/PU_to_PD.jpg}
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\vfill
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\subsection{Zeitverhalten CMOS Gatter}
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\includegraphics[width = 0.32\textwidth]{images/Laufzeit.jpg}
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Durchschnittliche Verzögerung: \eqbox{$t_d = \dfrac{t_{pHL} + t_{pLH}}{2}$}
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