307 lines
9.3 KiB
TeX
307 lines
9.3 KiB
TeX
\section{Gatter}
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\subsection{AND- und OR-Gatter}
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\begin{minipage}{0.27\linewidth}
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\subsubsection{AND}
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\begin{equation*}
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Z = A \land B
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\end{equation*}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC]
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\node[and gate] (and) at (0,0) {};
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\node[] (iA) at (-1, 0.4) {A};
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\node[] (iB) at (-1, -0.4) {B};
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\node[] (oZ) at (1, 0) {Z};
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\draw (iA.east) --++ (right:2mm) |- (and.input 1);
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\draw (iB.east) --++ (right:2mm) |- (and.input 2);
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\draw (and.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\vline \,
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\begin{minipage}{0.27\linewidth}
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\subsubsection{OR}
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\begin{equation*}
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Z = A \lor B
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\end{equation*}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC]
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\node[or gate] (or) at (0,0) {};
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\node[] (iA) at (-1, 0.4) {A};
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\node[] (iB) at (-1, -0.4) {B};
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\node[] (oZ) at (1, 0) {Z};
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\draw (iA.east) --++ (right:2mm) |- (or.input 1);
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\draw (iB.east) --++ (right:2mm) |- (or.input 2);
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\draw (or.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\begin{minipage}{0.4\linewidth}
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\begin{tabular}{|c c|c|c|} \hline
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A & B & AND & OR \\ \hline
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0 & 0 & 0 & 0 \\
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0 & 1 & 0 & 1 \\
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1 & 0 & 0 & 1 \\
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1 & 1 & 1 & 1 \\ \hline
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\end{tabular}
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\end{minipage}
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\subsection{NAND- und NOR-Gatter}
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\begin{minipage}{0.25\linewidth}
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\subsubsection{NAND}
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\begin{equation*}
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Z = \overline{A \land B}
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\end{equation*}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[nand gate] (nand) at (0,0) {};
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\node[] (iA) at (-0.8, 0.4) {A};
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\node[] (iB) at (-0.8, -0.4) {B};
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\node[] (oZ) at (0.8, 0) {Z};
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\draw (iA.east) --++ (right:1.5mm) |- (nand.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (nand.input 2);
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\draw (nand.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\vline \,
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\begin{minipage}{0.25\linewidth}
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\subsubsection{NOR}
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\begin{equation*}
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Z = \overline{A \lor B}
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\end{equation*}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[nor gate] (nor) at (0,0) {};
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\node[] (iA) at (-0.8, 0.4) {A};
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\node[] (iB) at (-0.8, -0.4) {B};
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\node[] (oZ) at (0.8, 0) {Z};
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\draw (iA.east) --++ (right:1.5mm) |- (nor.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (nor.input 2);
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\draw (nor.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\begin{minipage}{0.45\linewidth}
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\begin{tabular}{|c c|c|c|}
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\hline
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A & B & NAND & NOR \\
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\hline
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0 & 0 & 1 & 1 \\
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0 & 1 & 1 & 0 \\
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1 & 0 & 1 & 0 \\
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1 & 1 & 0 & 0 \\
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\hline
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\end{tabular}
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\end{minipage}
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\begin{minipage}{0.47\linewidth}
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\subsubsection{NAND}
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\includegraphics[height = 45mm]{images/nand.png}
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\end{minipage}
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\vline \,
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\begin{minipage}{0.47\linewidth}
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\subsubsection{NOR}
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\includegraphics[height = 45mm]{images/nor.png}
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\end{minipage}
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\subsection{NOT}
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\begin{minipage}{0.3\linewidth}
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\begin{equation*}
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Z = \overline{A}
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\end{equation*}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC]
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\node[not gate] (not) at (0,0) {};
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\node[] (iA) at (-0.8, 0) {A};
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\node[] (oZ) at (0.8, 0) {Z};
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\draw (iA.east) -- (not.input);
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\draw (not.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\begin{minipage}{0.25\linewidth}
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\begin{tabular}{|c|c|} \hline
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A & NOT \\ \hline
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0 & 1 \\
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1 & 0 \\ \hline
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\end{tabular}
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\end{minipage}
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\hfill
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\begin{minipage}{0.3\linewidth}
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\includegraphics[height = 25mm]{images/not.png}
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\end{minipage}
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\begin{minipage}{0.46\linewidth}
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\subsubsection{NOT aus NOR}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC]
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\node[nor gate] (gate) at (0,0) {};
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\node[] (iA) at (-1, 0) {A};
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\node[] (oZ) at (1, 0) {Z};
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\draw (iA.east) --++ (right:2mm) |- (gate.input 1);
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\draw (iA.east) --++ (right:2mm) |- (gate.input 2);
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\draw (gate.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\vline \,
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\begin{minipage}{0.46\linewidth}
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\subsubsection{NOT aus NAND}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC]
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\node[nand gate] (gate) at (0,0) {};
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\node[] (iA) at (-1, 0) {A};
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\node[] (oZ) at (1, 0) {Z};
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\draw (iA.east) --++ (right:2mm) |- (gate.input 1);
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\draw (iA.east) --++ (right:2mm) |- (gate.input 2);
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\draw (gate.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\vfill
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\subsection{XOR und XNOR}
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\begin{minipage}{0.47\linewidth}
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\subsubsection{XOR}
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\begin{tabular}{l l}
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$Z$ & $= A \oplus B$ \\
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& $= (A \land \overline{B}) \lor (\overline{A} \land B)$ \\
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\end{tabular}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[xor gate] (xor) at (0,0) {};
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\node[] (iA) at (-0.8, 0.4) {A};
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\node[] (iB) at (-0.8, -0.4) {B};
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\node[] (oZ) at (0.8, 0) {E};
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\draw (iA.east) --++ (right:1.5mm) |- (xor.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (xor.input 2);
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\draw (xor.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\vline \,
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\begin{minipage}{0.47\linewidth}
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\subsubsection{XNOR}
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\begin{tabular}{l l}
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$Z$ & $= \overline{A \oplus B}$ \\
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& $= (A \land B) \lor (\overline{A} \land \overline{B})$ \\
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\end{tabular}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[xnor gate] (xnor) at (0,0) {};
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\node[] (iA) at (-0.8, 0.4) {A};
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\node[] (iB) at (-0.8, -0.4) {B};
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\node[] (oZ) at (0.8, 0) {F};
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\draw (iA.east) --++ (right:1.5mm) |- (xnor.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (xnor.input 2);
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\draw (xnor.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\begin{center}
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\begin{tabular}{|c c|c|c|}\hline
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A & B & XOR & XNOR \\\hline
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0 & 0 & 0 & 1 \\
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0 & 1 & 1 & 0 \\
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1 & 0 & 1 & 0 \\
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1 & 1 & 0 & 1 \\\hline
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\end{tabular}
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\end{center}
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\subsection{Gatter aus NAND- und NOR-Gatter}
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\begin{minipage}{0.47\linewidth}
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\subsubsection{AND-Gatter aus NOR-Gatter}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[nor gate] (nor1) at (0,0) {};
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\node[nor gate] (nor2) at (0,-1.1) {};
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\node[nor gate] (nor3) at (1.1,-0.55) {};
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\node[] (iA) at (-0.8, 0) {A};
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\node[] (iB) at (-0.8, -1.1) {B};
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\node[] (oZ) at (2, -0.55) {Z};
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\draw (iA.east) --++ (right:1.5mm) |- (nor1.input 1);
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\draw (iA.east) --++ (right:1.5mm) |- (nor1.input 2);
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\draw (iB.east) --++ (right:1.5mm) |- (nor2.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (nor2.input 2);
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\draw (nor1.output) --++ (right:1.5mm) |- (nor3.input 1);
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\draw (nor2.output) --++ (right:1.5mm) |- (nor3.input 2);
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\draw (nor3.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\vline \,
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\begin{minipage}{0.47\linewidth}
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\subsubsection{OR-Gatter aus NAND-Gatter}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[nand gate] (nand1) at (0,0) {};
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\node[nand gate] (nand2) at (0,-1.1) {};
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\node[nand gate] (nand3) at (1.1,-0.55) {};
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\node[] (iA) at (-0.8, 0) {A};
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\node[] (iB) at (-0.8, -1.1) {B};
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\node[] (oZ) at (2, -0.55) {Z};
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\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 1);
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\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 2);
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\draw (iB.east) --++ (right:1.5mm) |- (nand2.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (nand2.input 2);
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\draw (nand1.output) --++ (right:1.5mm) |- (nand3.input 1);
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\draw (nand2.output) --++ (right:1.5mm) |- (nand3.input 2);
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\draw (nand3.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\end{minipage}
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\subsubsection{XOR Gatter}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[nand gate] (nand2) at (1.3,0) {};
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\node[nand gate] (nand3) at (1.3,-1.1) {};
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\node[nand gate] (nand1) at (0.2,-0.55) {};
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\node[nand gate] (nand4) at (2.4,-0.55) {};
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\node[] (iA) at (-0.8, 0.17) {A};
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\node[] (iB) at (-0.8, -1.27) {B};
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\node[] (oZ) at (3.3, -0.55) {Z};
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\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 1);
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\draw (iA.east) --++ (right:1.5mm) |- (nand2.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (nand1.input 2);
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\draw (iB.east) --++ (right:1.5mm) |- (nand3.input 2);
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\draw (nand1.output) --++ (right:1.5mm) |- (nand2.input 2);
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\draw (nand1.output) --++ (right:1.5mm) |- (nand3.input 1);
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\draw (nand2.output) --++ (right:1.5mm) |- (nand4.input 1);
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\draw (nand3.output) --++ (right:1.5mm) |- (nand4.input 2);
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\draw (nand4.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\subsubsection{XNOR Gatter}
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\begin{center}
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\begin{tikzpicture}[circuit logic IEC, thick]
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\node[nand gate] (nand2) at (1.3,0) {};
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\node[nand gate] (nand3) at (1.3,-1.1) {};
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\node[nand gate] (nand1) at (0.2,-0.55) {};
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\node[nand gate] (nand4) at (2.4,-0.55) {};
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\node[nand gate] (nand5) at (3.5,-0.55) {};
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\node[] (iA) at (-0.8, 0.17) {A};
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\node[] (iB) at (-0.8, -1.27) {B};
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\node[] (oZ) at (4.4, -0.55) {Z};
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\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 1);
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\draw (iA.east) --++ (right:1.5mm) |- (nand2.input 1);
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\draw (iB.east) --++ (right:1.5mm) |- (nand1.input 2);
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\draw (iB.east) --++ (right:1.5mm) |- (nand3.input 2);
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\draw (nand1.output) --++ (right:1.5mm) |- (nand2.input 2);
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\draw (nand1.output) --++ (right:1.5mm) |- (nand3.input 1);
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\draw (nand2.output) --++ (right:1.5mm) |- (nand4.input 1);
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\draw (nand3.output) --++ (right:1.5mm) |- (nand4.input 2);
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\draw (nand4.output) --++ (right:1.5mm) |- (nand5.input 1);
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\draw (nand4.output) --++ (right:1.5mm) |- (nand5.input 2);
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\draw (nand5.output) -- (oZ);
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\end{tikzpicture}
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\end{center}
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\vfill
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