\section{Gatter}

\subsection{AND- und OR-Gatter}

\begin{minipage}{0.27\linewidth}
	\subsubsection{AND}
	\begin{equation*}
		Z = A \land B
	\end{equation*}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC]
			\node[and gate] (and) at (0,0) {};
			\node[] (iA) at (-1, 0.4) {A};
			\node[] (iB) at (-1, -0.4) {B};
			\node[] (oZ) at (1, 0) {Z};
			\draw (iA.east) --++ (right:2mm) |- (and.input 1);
			\draw (iB.east) --++ (right:2mm) |- (and.input 2);
			\draw (and.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\vline \,
\begin{minipage}{0.27\linewidth}
	\subsubsection{OR}
	\begin{equation*}
		Z = A \lor B
	\end{equation*}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC]
			\node[or gate] (or) at (0,0) {};
			\node[] (iA) at (-1, 0.4) {A};
			\node[] (iB) at (-1, -0.4) {B};
			\node[] (oZ) at (1, 0) {Z};
			\draw (iA.east) --++ (right:2mm) |- (or.input 1);
			\draw (iB.east) --++ (right:2mm) |- (or.input 2);
			\draw (or.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\begin{minipage}{0.4\linewidth}
	\begin{tabular}{|c c|c|c|} \hline
		A & B & AND & OR \\ \hline
		0 & 0 & 0   & 0  \\
		0 & 1 & 0   & 1  \\
		1 & 0 & 0   & 1  \\
		1 & 1 & 1   & 1  \\ \hline
	\end{tabular}
\end{minipage}


\subsection{NAND- und NOR-Gatter}

\begin{minipage}{0.25\linewidth}
	\subsubsection{NAND}
	\begin{equation*}
		Z = \overline{A \land B}
	\end{equation*}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC, thick]
			\node[nand gate] (nand) at (0,0) {};
			\node[] (iA) at (-0.8, 0.4) {A};
			\node[] (iB) at (-0.8, -0.4) {B};
			\node[] (oZ) at (0.8, 0) {Z};
			\draw (iA.east) --++ (right:1.5mm) |- (nand.input 1);
			\draw (iB.east) --++ (right:1.5mm) |- (nand.input 2);
			\draw (nand.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\vline \,
\begin{minipage}{0.25\linewidth}
	\subsubsection{NOR}
	\begin{equation*}
		Z = \overline{A \lor B}
	\end{equation*}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC, thick]
			\node[nor gate] (nor) at (0,0) {};
			\node[] (iA) at (-0.8, 0.4) {A};
			\node[] (iB) at (-0.8, -0.4) {B};
			\node[] (oZ) at (0.8, 0) {Z};
			\draw (iA.east) --++ (right:1.5mm) |- (nor.input 1);
			\draw (iB.east) --++ (right:1.5mm) |- (nor.input 2);
			\draw (nor.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\begin{minipage}{0.45\linewidth}
	\begin{tabular}{|c c|c|c|}
		\hline
		A & B & NAND & NOR \\
		\hline
		0 & 0 & 1    & 1   \\
		0 & 1 & 1    & 0   \\
		1 & 0 & 1    & 0   \\
		1 & 1 & 0    & 0   \\
		\hline
	\end{tabular}
\end{minipage}

\begin{minipage}{0.47\linewidth}
	\subsubsection{NAND}
	\includegraphics[height = 45mm]{images/nand.png}
\end{minipage}
\vline \,
\begin{minipage}{0.47\linewidth}
	\subsubsection{NOR}
	\includegraphics[height = 45mm]{images/nor.png}
\end{minipage}


\subsection{NOT}

\begin{minipage}{0.3\linewidth}
	\begin{equation*}
		Z = \overline{A}
	\end{equation*}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC]
			\node[not gate] (not) at (0,0) {};
			\node[] (iA) at (-0.8, 0) {A};
			\node[] (oZ) at (0.8, 0) {Z};
			\draw (iA.east) -- (not.input);
			\draw (not.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\begin{minipage}{0.25\linewidth}
	\begin{tabular}{|c|c|} \hline
		A & NOT \\ \hline
		0 & 1   \\
		1 & 0   \\ \hline
	\end{tabular}
\end{minipage}
\hfill
\begin{minipage}{0.3\linewidth}
	\includegraphics[height = 25mm]{images/not.png}
\end{minipage}

\begin{minipage}{0.46\linewidth}
	\subsubsection{NOT aus NOR}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC]
			\node[nor gate] (gate) at (0,0) {};
			\node[] (iA) at (-1, 0) {A};
			\node[] (oZ) at (1, 0) {Z};
			\draw (iA.east) --++ (right:2mm) |- (gate.input 1);
			\draw (iA.east) --++ (right:2mm) |- (gate.input 2);
			\draw (gate.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\vline \,
\begin{minipage}{0.46\linewidth}
	\subsubsection{NOT aus NAND}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC]
			\node[nand gate] (gate) at (0,0) {};
			\node[] (iA) at (-1, 0) {A};
			\node[] (oZ) at (1, 0) {Z};
			\draw (iA.east) --++ (right:2mm) |- (gate.input 1);
			\draw (iA.east) --++ (right:2mm) |- (gate.input 2);
			\draw (gate.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\vfill


\subsection{XOR und XNOR}

\begin{minipage}{0.47\linewidth}
	\subsubsection{XOR}
	\begin{tabular}{l l}
		$Z$ & $= A \oplus B$                                         \\
		    & $= (A \land \overline{B}) \lor (\overline{A} \land B)$ \\
	\end{tabular}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC, thick]
			\node[xor gate] (xor) at (0,0) {};
			\node[] (iA) at (-0.8, 0.4) {A};
			\node[] (iB) at (-0.8, -0.4) {B};
			\node[] (oZ) at (0.8, 0) {E};
			\draw (iA.east) --++ (right:1.5mm) |- (xor.input 1);
			\draw (iB.east) --++ (right:1.5mm) |- (xor.input 2);
			\draw (xor.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\vline \,
\begin{minipage}{0.47\linewidth}
	\subsubsection{XNOR}
	\begin{tabular}{l l}
		$Z$ & $= \overline{A \oplus B}$                              \\
		    & $= (A \land B) \lor (\overline{A} \land \overline{B})$ \\
	\end{tabular}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC, thick]
			\node[xnor gate] (xnor) at (0,0) {};
			\node[] (iA) at (-0.8, 0.4) {A};
			\node[] (iB) at (-0.8, -0.4) {B};
			\node[] (oZ) at (0.8, 0) {F};
			\draw (iA.east) --++ (right:1.5mm) |- (xnor.input 1);
			\draw (iB.east) --++ (right:1.5mm) |- (xnor.input 2);
			\draw (xnor.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\begin{center}
	\begin{tabular}{|c c|c|c|}\hline
		A & B & XOR & XNOR \\\hline
		0 & 0 & 0   & 1    \\
		0 & 1 & 1   & 0    \\
		1 & 0 & 1   & 0    \\
		1 & 1 & 0   & 1    \\\hline
	\end{tabular}
\end{center}

\subsection{Gatter aus NAND- und NOR-Gatter}
\begin{minipage}{0.47\linewidth}
	\subsubsection{AND-Gatter aus NOR-Gatter}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC, thick]
			\node[nor gate] (nor1) at (0,0) {};
			\node[nor gate] (nor2) at (0,-1.1) {};
			\node[nor gate] (nor3) at (1.1,-0.55) {};
			\node[] (iA) at (-0.8, 0) {A};
			\node[] (iB) at (-0.8, -1.1) {B};
			\node[] (oZ) at (2, -0.55) {Z};
			\draw (iA.east) --++ (right:1.5mm) |- (nor1.input 1);
			\draw (iA.east) --++ (right:1.5mm) |- (nor1.input 2);
			\draw (iB.east) --++ (right:1.5mm) |- (nor2.input 1);
			\draw (iB.east) --++ (right:1.5mm) |- (nor2.input 2);
			\draw (nor1.output) --++ (right:1.5mm) |- (nor3.input 1);
			\draw (nor2.output) --++ (right:1.5mm) |- (nor3.input 2);
			\draw (nor3.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\vline \,
\begin{minipage}{0.47\linewidth}
	\subsubsection{OR-Gatter aus NAND-Gatter}
	\begin{center}
		\begin{tikzpicture}[circuit logic IEC, thick]
			\node[nand gate] (nand1) at (0,0) {};
			\node[nand gate] (nand2) at (0,-1.1) {};
			\node[nand gate] (nand3) at (1.1,-0.55) {};
			\node[] (iA) at (-0.8, 0) {A};
			\node[] (iB) at (-0.8, -1.1) {B};
			\node[] (oZ) at (2, -0.55) {Z};
			\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 1);
			\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 2);
			\draw (iB.east) --++ (right:1.5mm) |- (nand2.input 1);
			\draw (iB.east) --++ (right:1.5mm) |- (nand2.input 2);
			\draw (nand1.output) --++ (right:1.5mm) |- (nand3.input 1);
			\draw (nand2.output) --++ (right:1.5mm) |- (nand3.input 2);
			\draw (nand3.output) -- (oZ);
		\end{tikzpicture}
	\end{center}
\end{minipage}
\subsubsection{XOR Gatter}
\begin{center}
	\begin{tikzpicture}[circuit logic IEC, thick]
		\node[nand gate] (nand2) at (1.3,0) {};
		\node[nand gate] (nand3) at (1.3,-1.1) {};
		\node[nand gate] (nand1) at (0.2,-0.55) {};
		\node[nand gate] (nand4) at (2.4,-0.55) {};
		\node[] (iA) at (-0.8, 0.17) {A};
		\node[] (iB) at (-0.8, -1.27) {B};
		\node[] (oZ) at (3.3, -0.55) {Z};
		\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 1);
		\draw (iA.east) --++ (right:1.5mm) |- (nand2.input 1);
		\draw (iB.east) --++ (right:1.5mm) |- (nand1.input 2);
		\draw (iB.east) --++ (right:1.5mm) |- (nand3.input 2);
		\draw (nand1.output) --++ (right:1.5mm) |- (nand2.input 2);
		\draw (nand1.output) --++ (right:1.5mm) |- (nand3.input 1);
		\draw (nand2.output) --++ (right:1.5mm) |- (nand4.input 1);
		\draw (nand3.output) --++ (right:1.5mm) |- (nand4.input 2);
		\draw (nand4.output) -- (oZ);
	\end{tikzpicture}
\end{center}
\subsubsection{XNOR Gatter}
\begin{center}
	\begin{tikzpicture}[circuit logic IEC, thick]
		\node[nand gate] (nand2) at (1.3,0) {};
		\node[nand gate] (nand3) at (1.3,-1.1) {};
		\node[nand gate] (nand1) at (0.2,-0.55) {};
		\node[nand gate] (nand4) at (2.4,-0.55) {};
		\node[nand gate] (nand5) at (3.5,-0.55) {};
		\node[] (iA) at (-0.8, 0.17) {A};
		\node[] (iB) at (-0.8, -1.27) {B};
		\node[] (oZ) at (4.4, -0.55) {Z};
		\draw (iA.east) --++ (right:1.5mm) |- (nand1.input 1);
		\draw (iA.east) --++ (right:1.5mm) |- (nand2.input 1);
		\draw (iB.east) --++ (right:1.5mm) |- (nand1.input 2);
		\draw (iB.east) --++ (right:1.5mm) |- (nand3.input 2);
		\draw (nand1.output) --++ (right:1.5mm) |- (nand2.input 2);
		\draw (nand1.output) --++ (right:1.5mm) |- (nand3.input 1);
		\draw (nand2.output) --++ (right:1.5mm) |- (nand4.input 1);
		\draw (nand3.output) --++ (right:1.5mm) |- (nand4.input 2);
		\draw (nand4.output) --++ (right:1.5mm) |- (nand5.input 1);
		\draw (nand4.output) --++ (right:1.5mm) |- (nand5.input 2);
		\draw (nand5.output) -- (oZ);
	\end{tikzpicture}
\end{center}
\vfill
